About

We are excited to announce the upcoming First Global RISC-V Open Workshop (GROW 2025), an event focused on advancing RISC-V technologies. GROW serves as a venue for researchers, practitioners, and industry experts to present innovative ideas, groundbreaking research, and emerging trends that shape the design, optimization, and implementation of modern RISC-V systems. Selected speakers from across the globe will be invited to present their state-of-the-art work on RISC-V technologies and EDA tools. World-class keynote speakers will present their long-term views of the RISC-V technologies.

Location

The event will take place at the University of São Paulo INOVA Autitorium, at Av. Prof. Lúcio Martins Rodrigues, 370, São Paulo.

Keynote Speakers

Wednesday Lunch Keynote (Remote)

David Patterson ( UC Berkeley )

• David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1976. Dave's research style is to identify critical questions for the IT industry and gather inter-disciplinary groups of faculty and graduate students to answer them. The answer is typically embodied in demonstration systems, and these demonstration systems are later mirrored in commercial products. In addition to research impact, these projects train leaders of our field. The best known projects were Reduced Instruction Set Computers (RISC), Redundant Array of Inexpensive Disks (RAID), and Networks of Workstations (NOW), each of which helped lead to billion dollar industries. A measure of the success of projects is the list of awards won by Patterson and as his teammates: the ACM A.M. Turing Award, the C & C Prize, the IEEE von Neumann Medal, the IEEE Johnson Storage Award, the SIGMOD Test of Time award, the ACM-IEEE Eckert-Mauchly Award, and the Katayanagi Prize. He was also elected to both AAAS societies, the National Academy of Engineering, the National Academy of Sciences, the Silicon Valley Engineering Hall of Fame, and to be a Fellow of the Computer History Museum. The full list includes about 40 awards for research, teaching, and service. In his spare time he coauthored seven books---including two with John Hennessy who is past President of Stanford University and with whom he shared the Turing Award--- Patterson also served as Chair of the Computer Science Division at UC Berkeley, Chair of the Computing Research Association, and President of ACM.

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Monday Morning Keynote

Yungang Bao ( ICT-CAS )

• Yungang Bao has devoted himself to cutting-edge technology research and prototype system development, including a Hybrid Memory Trace Toolkit (HMTT), memory DMA Cache for I/O, multithreaded benchmark suite for Shared-Memory Computers (PARSEC 3.0), and Labeled von Neumann Architecture (LvNA), etc, which have been applied in Huawei, Alibaba, Intel and Microsoft. He leads the team to work on a series of open-source chip research project, including the open source high-performance RISC-V processor core -"Xiangshan", the "One Chip One Student" plan, and the System Emulation and prototyping for RISC-V Environment (SERVE), etc., His team has become one of the most active research teams in open-source processor chips in the world. Yungang Bao has over 70 publications appeared in several top conferences and journals such as ASPLOS, CACM, HPCA, ISCA, SIGCOMM and NSDI. And he received the CCF-IEEE CS Young Scientist Award.

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EDA in the Era of AI: What Large Models Bring to Chip Design

Qiang Xu ( CUHK )

• Qiang Xu is a Professor at The Chinese University of Hong Kong. He also serves as the Chief Scientist of National Technology Innovation Center for EDA, China. His current research interests are in the broad areas of AI and EDA. He has published 200+ papers with over 10,000 citations, including several best papers at prestigious conferences and an ICCAD Ten Year Retrospective Most Influential Paper. He has supervised ~20 Ph.D. dissertations, and his students have won several Outstanding Ph.D. Dissertation Awards or Nominations.

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Monday Afternoon Keynote

Andrea Gallo ( RISC-V International )

• Andrea Gallo heads up the Technical Activities at RISC-V International with a mission to facilitate the technical vision, cultivate stakeholder engagement, and drive the strategy in a deeply engaged collaboration with RISC-V members across workgroups and committees and growing the adoption of the RISC-V Instruction Set Architecture. Prior to RISC-V International, Andrea held multiple roles at Linaro starting all Arm datacenter engineering activities ground up from firmware to complex cloud workloads, later as VP of Segment Groups he oversaw verticals from IoT to HPC including smartphones, and AI/ML. In his last years at Linaro he served as executive VP of Business Development, managing all membership contracts and starting new collaborative projects from automotive to Windows on Arm. Prior to Linaro, Andrea was Fellow at ST-Ericsson for smartphones and application processors and served as the first member representative in the Linaro TSC. Over the years at STMicroelectronics he consistently led the optimisation of hardware-software architectures for new ICs and set up remote teams in India. Andrea holds a University Degree in Telecommunication and speaks fluent French and English, in addition to his native Italian.

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Monday Lunch Keynote (Recorded Interview)

Luca Benini ( ETH Zurich )

• Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. He has been visiting professor at Stanford University, IMEC, EPFL. He served as chief architect in STmicroelectronics France. Dr. Benini's research interests are in energy-efficient parallel computing systems, smart sensing micro-systems and machine learning hardware. He has published more than 1000 peer-reviewed papers and five books. He is an ERC-advanced grant winner, a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award, the 2020 EDAA achievement Award, the 2020 ACM/IEEE A. Richard Newton Award and the 2023 IEEE CS E.J. McCluskey Award.

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CX: The Magna Carta for Custom Instructions in RISC-V

Guy Lemieux ( UBC )

• Guy Lemieux is a Professor in the Department of Electrical and Computer Engineering at The University of British Columbia (UBC). His main research is in the design of FPGAs and CAD tools. His interests include FPGA architecture and CAD, FPGA and VLSI circuit design, computer architecture, and parallel computing systems. His work on interconnect design for FPGAs resulted in a book, published in 2003. He received a Best Paper Award at the 2004 IEEE International Conference on Field-Programmable Technology. He received a Bronze Leaf Certificate paper award at the 2008 CMC Microsystems and Nanoelectronics Research Conference. Some of his past work on multiprocessing can be found at the University of Toronto.

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PUPPY: a RISC-V MCU for IoT applications

Marcelo Zuffo ( USP )

• Marcelo Knörich Zuffo is a Full Professor of Electrical Engineering at the University of São Paulo (USP), where he teaches in the Department of Electronic Systems Engineering at the Polytechnic School. He holds a master’s and a PhD in Electrical Engineering. He conducts research at the Laboratory of Integrated Systems (LSI), focusing on interactive media technologies, digital health, high-performance computing, virtual reality, computer graphics, and data visualization. In 2001, he developed Brazil’s first fully immersive virtual reality system, known as CAVERNA Digital. He is the scientific coordinator of the Testing and Auditing Laboratory (LEA) for Brazil’s digital certification system (ICP-Brasil). Since 2011, he has led the Interdisciplinary Center for Interactive Technologies at USP and helped coordinate the Inspire project, a low-cost emergency ventilator developed in response to the COVID-19 pandemic. He also serves as the director of INOVA USP, the university’s innovation center.

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When AI Hardware Meets Compiler Optimization

Guido Araujo ( UNICAMP )

• Guido Araujo received his PhD in Electrical Engineering from Princeton University. He is a Full Professor at the Institute of Computing at UNICAMP, and served as an Adjunct Professor of Computer Science at the University of Alberta. His main research interests are in code optimization, parallel programming, computer architecture, and hardware acceleration for AI, developed in close cooperation with Microsoft, Intel, Samsung, LGE, Xilinx, and universities in the USA and Canada. His research resulted in more than 120 international publications and six Best Paper Awards. His students were awarded three times the Best Dissertation Award from the Brazilian Computer Society (SBC), and the Ministry of Education Thesis Award (CAPES). He was also awarded twice the Zeferino Vaz Academic Recognition Award from UNICAMP, for his contributions to research and teaching in Computing, and the UNICAMP Inventors Award. He serves as a member of the IEEE MICRO Editorial Board and of the Technical Steering Committee of RISC-V International, representing the Brazilian Ministry of Science Technolgy and Innovation (MCTI). He was co-founder of companies Kryptus and Idea!

Program